As is known, in the context of storage systems, the need is felt to reach high storage capacities with high data-transfer rates (bitrates), while at the same time reducing the manufacturing costs. Storage systems currently most widely used, namely, hard-disk drives (with miniaturized dimensions) and flash RAMS, present intrinsic technological limits with respect to the increase of data-storage capacity and of read/write speed, as well as reduction of their dimensions.
Amongst existing technologies, storage systems that use a storage medium made of ferroelectric material, in which reading/writing of individual bits is made by interacting with the ferroelectric domains of the ferroelectric material, are very promising.
A ferroelectric material possesses a spontaneous polarization which can be reversed by an applied electrical field. As shown in FIG. 1, the material moreover presents a hysteresis cycle in the diagram of the polarization charge Q (or, equivalently, of the polarization P) as a function of the applied voltage V, and by exploiting this, it is possible to store information in the form of bits. In particular, in the absence of a biasing voltage imparted on the medium (V=0), there exist two points of the diagram in the stable state (designated by “b” and “e”) that have different polarization, in particular equal and opposite. The points can remain in the stable state even for some years, thus maintaining the binary datum stored (for example, point “b”, with positive charge +QH, corresponds to a “0”, whereas point “e”, with negative charge −QH, corresponds to a “1”).
The writing operations envisage application to the ferroelectric medium of a positive or negative) voltage higher than a coercive voltage Vcoe characteristic of the ferroelectric material. In this case, a positive charge +QH, or negative charge −QH (this basically corresponds to a displacement along the diagram from point “e” to point “b” passing through point “a”, or else from point “b” to point “e” passing through point “d”) is stored in the material. A voltage having an absolute value that is lower than the coercive voltage V, does not, instead, cause a stable variation of the charge stored.
The data-reading techniques commonly used are based on a destructive operation, which envisages erasure of the data read. In summary, a (positive or negative) voltage having an amplitude greater than that of the coercive voltage Vcoe is applied to the ferroelectric material, thus performing in practice a writing operation, and the occurrence or otherwise of a reversal of polarity of the ferroelectric material is detected. For this purpose, the existence or not of an appreciable current that flows in the ferroelectric material is detected. Clearly, the application of a positive (or negative) voltage causes reversal of just the ferroelectric domains in which a negative charge −QH (or positive charge +QH) has previously been stored.
The main problem of the reading technique is linked to the fact that the reading operations are destructive; i.e., they imply removal of the information stored previously and hence the impossibility of carrying out subsequent readings of the data themselves, without there having previously carried out a re-writing of the data read. In fact, reading of a portion of the memory corresponds to writing in the memory portion of a sequence of charges that are all positive (or all negative, in the case where a negative reading voltage is used). Consequently, during reading the flow of the data read is stored in a memory buffer, and a writing operation is then necessary for restoring the original information.
The reading technique entails a considerable expenditure of time and power, and basically creates a bottleneck for current ferroelectric storage systems, in particular as regards bitrate.
In order to overcome these issues some techniques of non-destructive reading of the data stored have been devised.
For example in Cho et al., “Terabit inch−2 ferroelectric data storage using scanning nonlinear dielectric microscopy nanodomain engineering system”, Nanotechnology No. 14, 2003, 637-642, Institute of Physics Publishing, a sinusoidal signal is applied to a ring electrode, which induces an oscillation in a resonant circuit that includes the ferroelectric medium in which the information bit is stored. A demodulator detects the harmonics of the induced oscillation, the phases of which are correlated to the information bit stored, on account of the different behaviour of the high-order nonlinear permittivities of the ferroelectric material in the stable points of the polarization diagram.
In Kato et al., “0.18-μm nondestructive readout FeRAM using charge compensation technique”, IEEE Transactions on electron devices, Vol. 52 No. 12, December 2005, a reading circuit is described, which envisages a connection in series of a ferroelectric capacitor (constituted by the storage medium) to the gate terminal of a reading MOS transistor. By applying a reading pulse, the charge stored in the capacitor biases the gate terminal of the MOS transistor, in a different way according to the polarization state stored previously, thus varying the conductivity of the conduction channel thereof. Next, the datum stored is read by detecting the current that flows between the current-conduction terminals of the transistor itself, in a static way, by a sense amplifier.
The aforementioned reading techniques, albeit presenting the advantage of not being destructive and hence not requiring re-writing of the data read, are not altogether satisfactory with regard to the constructional complexity and their operation.
Other documents that describe memories comprising ferroelectric elements and corresponding read/write methods are the patents Nos. U.S. Pat. No. 5,086,412, U.S. Pat. No. 6,819,583, and U.S. Pat. No. 4,888,733. However, each of the memory cells according to these documents comprises one or more transistors for direct addressing of the memory cell, and at least one additional ferroelectric capacitor for storage of the charge that represents the logic information (bit “1” or bit “0”) to be stored. Also the above approaches are not optimal in terms of occupation of area and operation. For example, some of these memories present problems of coupling between adjacent cells during the writing operations.